Data processing systems, such as personal computers and workstations, as well as other modern electronic equipment, generally rely on regulated power supplies for the biasing and operation of integrated circuits contained therein. Such regulated power supplies provide stable power supply bias voltages to the various circuit functions in the system, in an effort to reduce loss of data or other functional system errors caused by unstable or varying power supply voltages.
Unstable or indeterminate operation of the components in such systems can also occur during transient operating events, particularly power-up. In addition, a fault in the regulated power supply which causes overvoltage or undervoltage power supply levels can, if applied to system components while operating, cause temporary or permanent failures of the components. Accordingly, power supply monitoring and control circuits have been used in personal computers, workstations, and other electronic systems to monitor the output of the regulated power supply in the system, and to disable components from operating when the output voltages are outside of the desired range.
An example of a prior power supply supervisor circuit is described in our U.S. Pat. No. 4,591,171, issued Aug. 21, 1990, assigned to Compaq Computer Corporation, and incorporated herein by this reference. This prior power supply supervisor circuit monitors the output of a regulated power supply, and disables the system central processing unit (CPU) in the event of overvoltage, undervoltage, or excessively high current output from the power supply. In addition, this power supply supervisor circuit also generates a shutdown signal to the power supply itself in such events, preventing further damage to the data processing system. This circuit includes delay circuits so that the undervoltage condition which occurs during power-up of the regulated power supply does not result in a shutdown signal to the power supply, while immediately producing the shutdown signal in the event of overvoltage and overcurrent conditions occurring during power-up. A delay circuit is also provided to delay the "power-good" signal to the CPU and other components for a selected period of time, allowing the power supply output voltages to stabilize after power-up.
In the circuit described in said U.S. Pat. No. 4,951,171, the power-up delay (i.e., the time period during which undervoltage conditions will not generate a shutdown signal) is designed to be longer than the power-good delay (i.e., the delay of the "power-good" signal), thus ensuring that the power supply does not shut down prematurely during power-up. This configuration is adequate for many components and systems, as many undervoltage conditions on power-up will cause an overcurrent event, responsive to which the circuit immediately issues the shutdown signal. However, in more recent systems, the CPU and other circuit components are fabricated with higher density processes, potentially increasing their sensitivity to undervoltage conditions. Undervoltage conditions of even brief duration can result in damage to such circuits. In particular, some complementary metal-oxide-semiconductor (CMOS) components can enter a "latchup" condition if the negative "back-bias" power supply voltage is inadequate. In these systems, rapid shutdown of the regulated power supply in an undervoltage condition can prevent permanent damage to the integrated circuit components.
In addition, certain short circuit conditions can be present in the system which may not be detected by the circuit of said U.S. Pat. No. 4,951,171. For example, in the circuit of said U.S. Pat. No. 4,951,171, overcurrent detection is not necessarily provided for all power supplies, particularly those which are expected to have minimal load; as such, an output of the regulated power supply may have a "dead" short to ground prior to power-up which may go undetected by the power supply supervisor circuit. Furthermore, in this prior circuit, a short undervoltage condition may occur between the time that the power-good signal is issued and the expiration of the power-up delay. In either of these cases, the undervoltage condition may cause stress or damage to modern sensitive integrated circuit components, but would go undetected by the supervisor circuit.
It is therefore an object of this invention to provide a power supply supervisor circuit for which the power-up delay can be independently selected from the power-good delay.
It is a further object of this invention to provide a power supply supervisor circuit for which the power-up delay can be shorter than the power-good delay, so that a power supply shutdown signal can be generated responsive to an undervoltage condition on power-up.
It is a further advantage of the present invention to provide such a power supply supervisor circuit having an active output driver for generating the power-good signal, improving the ability of the system to quickly respond to successful power-up.
Other objects and advantages of this invention will become apparent to those of ordinary skill in the art having reference to the following specification, together with the drawings.